International Research conference of SLTC 2020 - IRC 2020
http://repo.sltc.ac.lk/${dspace.ui}/handle/1/87
2024-03-23T19:13:12ZFast Data Compression Using Huffman-Based Tree Structure
http://repo.sltc.ac.lk/${dspace.ui}/handle/1/135
Fast Data Compression Using Huffman-Based Tree Structure
Lakmali, Dilini; Waidyarathna, Uththara; De Silva, Dilanka; Sivapatham, Sayansi
There is a high demand to improve the encoding
and decoding speed of data compression among modern users.
When a binary Huffman code is used, it requires more time to
compress or decompress every single bit. The technique which
is being proposed in this paper is a new Huffman-Based tree
structure instead of a consistent binary tree to reduce decoding
time complexity. Since the traversing time depends on the height
of the tree, the proposed tree structure provides a smaller height
than the height of the regular binary tree. The performance
of the regular Huffman tree technique and proposed technique
is evaluated in terms of the decoding time. According to the
results analyzed, the proposed technique outperforms the current
Binary tree technique in terms of decompression speed while the
compression performance remains nearly the same.
2020-01-01T00:00:00ZNew Approach for Channel Encoding and Decoding Using (8,4) Extended Hamming Code
http://repo.sltc.ac.lk/${dspace.ui}/handle/1/134
New Approach for Channel Encoding and Decoding Using (8,4) Extended Hamming Code
Mushfick, M.M.M.; Puspatheepan, A.; De Silva, Dilanka
In this paper, the Channel Encoding and Decoding
process is implemented using the (8,4) Extended Hamming code,
in Quartus II 13.0 design software through VHDL program ming language and ModelSim-Altera software for simulating
the circuit designs. With a minimum Hamming distance of
four, Single-Error Correction and Double-Error Detection (SEC DED) can be achieved. Dissipation of power through heat and
high processing time are the major shortcomings of using non reversible logic gates. The combinational logic gate designs are
built using reversible logic to reduce dissipation of heat and
processing delay. FPGAs are preferred over micro-controllers for
the implementation of the designs, due to low signal processing
latency and high parallel processing capability. The detection
and correction of errors is achieved by following a new effective
concept/algorithm to achieve SEC-DED at the decoder. The
hardware implementation of the prototype was done using the
Altera DE0-Nano FPGA board
2020-01-01T00:00:00ZA Deep Learning Based Approach for the Classification of Diabetic Retinopathy in Human Retina
http://repo.sltc.ac.lk/${dspace.ui}/handle/1/133
A Deep Learning Based Approach for the Classification of Diabetic Retinopathy in Human Retina
Vimukthi, Yasodha; Kodikara, Nihal; Nanayakkara, Lakshika
Diabetic Retinopathy, a common diabetes
complication causes damages to the blood vessels of light
sensitive tissues in the human retina. Due to the limitations in
the manual screening process, there exists a compelling
requirement of an automated approach for the Diabetic
Retinopathy screening which can be applied regularly and in
abundance in any kind of a healthcare environment. This paper
suggests a Deep Learning based automated approach to classify
retinal fundus images into five major severity levels while
focusing on achieving the optimal accuracy-efficiency balance in
performance. In the classification task, a lightweight
Convolutional Neural Network (CNN) model with only 6
convolutional layers was suggested to classify retinal fundus
images to five major severity levels. CNN refinements such as
Hyperparameter Tuning, Regularization and Data
Augmentation were applied to increase the model accuracy. The
suggested model achieved an Accuracy of 72.28%, a Sensitivity
of 71.12% and a Specificity of 93.1% for a testing dataset of 267
retinal fundus images from Kaggle and Messidor-2 datasets. By
comparing with four pre-trained CNN models VGG16,
ResNet50, InceptionV3 and Xception, it was observed that the
accuracy of the suggested model is slightly lesser than that of
VGG16 and ResNet50 models. However, the number of FLOPs
in the suggested model is 23 times lesser than VGG16 and 6
times lesser than ResNet50, indicating that the suggested model
is more efficient than the mentioned pre-trained models. The
accuracy of the suggested model can be further improved
without increasing the number of FLOPs by increasing the
number of training data samples
2020-01-01T00:00:00ZPerformance Analysis of the SLIPT Architectures
http://repo.sltc.ac.lk/${dspace.ui}/handle/1/132
Performance Analysis of the SLIPT Architectures
Morapitiya, Sumali S.; Leelarathna, T.W.W.; Jayakody, Dushantha Nalin K.; Weerasuriya, R.U.
Recently, The study builds on Simultaneous Light wave Information and Power Transfer (SLIPT) has become a
hot topic among the research community. The importance of the
SLIPT is to harvest energy using light sources while decoding
the information. In this approach, we present the mathematical
framework for the Power Splitting (PS) based SLIPT system
and study the performance of the PS-SLIPT and time switching
(TS)-SLIPT architectures. Moreover, we quantitatively studied
the harvested energy with different Field of View (FoV) angles
of the Light Emitting Diode (LED) and the Photodiode (PD).
In addition, we considered the amount of harvested energy for
different Direct Current (DC) values. Overall, this paper con cludes that the FoV and DC bias signals are directly affected by
SLIPT systems. Using numerical simulations, we demonstrated
the performance of the both architectures to enhance the QoS
of data rate, amount of harvested energy and trustworthiness of
the information.
2020-01-01T00:00:00Z