Abstract:
In this paper, the Channel Encoding and Decoding
process is implemented using the (8,4) Extended Hamming code,
in Quartus II 13.0 design software through VHDL program ming language and ModelSim-Altera software for simulating
the circuit designs. With a minimum Hamming distance of
four, Single-Error Correction and Double-Error Detection (SEC DED) can be achieved. Dissipation of power through heat and
high processing time are the major shortcomings of using non reversible logic gates. The combinational logic gate designs are
built using reversible logic to reduce dissipation of heat and
processing delay. FPGAs are preferred over micro-controllers for
the implementation of the designs, due to low signal processing
latency and high parallel processing capability. The detection
and correction of errors is achieved by following a new effective
concept/algorithm to achieve SEC-DED at the decoder. The
hardware implementation of the prototype was done using the
Altera DE0-Nano FPGA board
